During the past decade, peripheral component interconnect (PCI) has provided a very successful general purpose input/output (I/O) interconnect standard. PCI is a general purpose I/O interconnect standard that utilizes PCI signaling technology, including a multi-drop, parallel bus implementation. Unfortunately, traditional multi-drop parallel bus technology is approaching its practical performance limits. In fact, the demands of emerging and future computing models exceed the bandwidth and scalability limits that are inherent in multiple drop, parallel bus implementations.
Meeting future system performance needs requires I/O bandwidth that can scale with processing and application demands. Fortunately, technology advances in high speed point-to-point interconnects are enabling system designers to break away from the bandwidth limitations of multiple drop, parallel buses. To this end, system designers have discovered a high-performance, third generation I/O (3GIO) interconnect that will serve as a general purpose I/O interconnect for a wide variety of future computing and communications platforms.
PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms and rolls them into a common scalable and extensible I/O industry specification. The PCI Express basic physical layer consists of a differential transmitter pair and a differential receiver pair. As such, dual simplex data on these point-to-point connection, referred to herein as a “point-to-point link,” is self-clocked, for such point-to-point (P2P) links, bandwidth increases linearly with interconnect (link) width and frequency. In addition, PCI Express also provides a message space within its protocol that is used to implement legacy side band signals. As a result, a further reduction of signal pins produces a very low pin count connection for components and adapters.
Unfortunately, the use of a differential transmitter and receiver pair is a drastic deviation from traditional PCI. As a result, many link mode combinations are now possible, thus creating new and challenging complexities for validation of such interfaces.
Furthermore, as point-to-point link speeds increase, it becomes more difficult to guarantee operation of the link by simply writing a link specification. Link-based systems such as those based on PCI-E and, for example, common system interconnect (CSI), have a link training mechanism where for example, the transmitter transmits a “compliance pattern.” As described herein, a compliance pattern refers to a sequence of bits that characterize the transmitter to generate the worst case eye diagram. Link training, may further include negotiated link widths, link speed and other like link configuration information. Hence, merely providing a link specification does not ensure correct operation of point-to-point links.